The difference between an orbit that lasts 5 years and one that lasts a hundred is approximately 100-200km, the limit is quite sharp and actually quite tricky to get exactly right. That will cost you about a millisecond or two in latency tops. It is more likely that SpaceX is required to adhere to rules made by the FCC/FAA.

Indeed, because those two things were only exemplary, meaning they would be indicative of your system having a bottleneck in almost all types workloads. Supported by the generally higher perforance in 64-bit mode.

Clearly you can address more bytes than your data bus width. But then why all the “hacks” on 32-bit architectures? Like the 36-bit address bus via memory mapping on SPARCv8 instead of using paired index registers ( or ARMv7 width LPAE). From a perfomance perspective using an address width that is not the native register width/ internal data bus width is an issue. For a significant subset of operations multiple instructions are required instead of one.

Also is your comment about turing completeness to be taken seriously? We are talking about performance and practicality. Go ahead and crunch on some 64-bit floats using purely 8-bit arithmetic operations (or even using vector registers). Of course you can, but the point is that a suitable word size is more effective for certain computational tasks. For operations that are done frequently, they should ideally be done at native data-bus width. Vectored operations will also cost performance.

I am unsure about the historical reasons for moving from 32-bit to 64-bit, but wouldnt the address space be a significantly larger factor? Like you said, CPUs have had vectoring instructions for a long time, and we wouldn’t move to 128-bit architectures just to be able to compute with numbers of those size. Memory bandwidth is, also as you say, limited by the bus widths and not the processor architecture. IMO, the most important reason that we transitioned to 64-bit is primarily for the larger address address space without having to use stupidly complex memory mapping schemes. There are also some types of numbers like timestamps and counters that profit from 64-bit, but even here I am not sure if the conplex architecture would yield a net slowdown or speedup.

To answer the original question: 128 bits would have no helpful benefit for the address space (already massive) and probably just slow everyday calculations down.

Rotary engines were never used for helicopters AFAIK. Maybe there are some niche designs

Yup, I know, it doesnt check out at all, you wouldn’t put a rotary on a helicoptor. But “rotary” engines were indeed used on aircraft, since they also refer to a radial cylinder configuration where the engine housing moves and the axis is fixed. So I think it’s likely they were referring to the common WWI plane engine. I didnt think of a wankel at all till you mentioned it! Interestingly enough, modern wankel engines are also sold for helicopters.

I’m a little confused, aren’t they just referring to aircraft rotary engines with the cylinders arranged radially? Or what’s the triggering part?

Huh. Apparently we justed needed to start a new platform to start dropping the real life pro tips. Seriously, where have you guys been keeping these??!?